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Packaging Integrated Circuit

IP.com Disclosure Number: IPCOM000073962D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Ross, RF: AUTHOR

Abstract

Shown is a package for containing and making electrical connection to an integrated circuit. The method consists of mounting integrated circuit 10 in a recessed area on substrate 12. Substrate 12 has deposited thereon electrical circuit paths 14. These paths merely provide connection between nodes 16 and an area 18 immediately adjacent the chip 10.

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Packaging Integrated Circuit

Shown is a package for containing and making electrical connection to an integrated circuit. The method consists of mounting integrated circuit 10 in a recessed area on substrate 12. Substrate 12 has deposited thereon electrical circuit paths 14. These paths merely provide connection between nodes 16 and an area 18 immediately adjacent the chip 10.

To interconnect the circuit paths 14 and the integrated circuit chip, wires 20 are bonded between areas 18 at the edge of the chip to connections on the chip. After the wires 20 have been bonded between the areas 18 and the chip 10, the upper substrate 12 may then be laid on top of the lower substrate 22.

Lower substrate 22 contains pins 24 which extend through the substrate to solder coating 26 on top of pins 24. When substrate 12 is laid over on substrate 22, the solder coating 26 of each pin 24 makes electrical contact with each node 16 on the upper substrate. The package may then be fired in a furnace to solder the pins 24 to nodes 16. Packing is completed by placing a can over the two substrates now interconnected and sealing the entire package.

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