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Monolithic Read Only Storage Circuit

IP.com Disclosure Number: IPCOM000073968D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Cross, JL: AUTHOR

Abstract

A high-speed monolithic read-only storage circuit is shown. The read-only storage apparatus comprises a plurality of storage arrays of m by n bits. The array comprises m...n transistors 10, each having a common collector so that all the transistors can be fabricated as monolithic integrated transistors formed in a single isolation region 12. During manufacture of the array each emitter of transistor 10 is either connected or not to its appropriate emitter rail 18, according to a particular desired bit pattern. Information is then determined during the read out of the storage device by sensing whether or not current flows through a particular device at the intersection of two selected base and emitter rails. To accomplish the bit sensing, an additional array of transistors 14 is produced in a special isolation region 16.

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Monolithic Read Only Storage Circuit

A high-speed monolithic read-only storage circuit is shown. The read-only storage apparatus comprises a plurality of storage arrays of m by n bits. The array comprises m...n transistors 10, each having a common collector so that all the transistors can be fabricated as monolithic integrated transistors formed in a single isolation region 12. During manufacture of the array each emitter of transistor 10 is either connected or not to its appropriate emitter rail 18, according to a particular desired bit pattern. Information is then determined during the read out of the storage device by sensing whether or not current flows through a particular device at the intersection of two selected base and emitter rails. To accomplish the bit sensing, an additional array of transistors 14 is produced in a special isolation region 16. The common collector point for the array is connected to a reference point such as ground and a voltage Vref is connected to the common base node of the transistors 14. Bit sensing then takes place at the common collector node 22 of transistors 14 so that the addressed bit is sensed by an uplevel voltage to turn on one of transistors 20 to switch the common current sink 24 into the desired emitter rail. The uplevel voltage required from the emitter decode must be sufficiently negative to prevent saturation of transistors 20. This technique of bit selection permits the use of only one current sink per bit array...