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Transistor Structure

IP.com Disclosure Number: IPCOM000073978D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+2]

Abstract

The use of inversely operated transistors often results in considerable silicon area savings with high-density integrated circuits, however, it is limited by the relatively low-current gain of such devices. Therefore, methods of improving the inverse transistor characteristics are required which can be implemented without changing the existing processing steps.

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Transistor Structure

The use of inversely operated transistors often results in considerable silicon area savings with high-density integrated circuits, however, it is limited by the relatively low-current gain of such devices. Therefore, methods of improving the inverse transistor characteristics are required which can be implemented without changing the existing processing steps.

The drawing shows the vertical structure of an NPN transistor which is characterized by a relatively large inverse current gain. It consists of a p- substrate, a first buried layer N/+/1, a first epitaxial layer N2, a second buried layer N/+/3, a second epitaxial layer N4, a p-diffusion layer, and two N/+/ diffusion layers N/+/5 and N/+/6 which are carried out simultaneously. The buried layer N/+/3 has been omitted underneath the N/+/6 collector area, but completely surrounds the p-diffusion area outside this collector area. Additionally, an N/+/5 diffused ring surrounds the p-diffusion on its lateral side. Those heavily doped N/+/ rings will reduce the carrier injection outside the area A because the threshold voltage of a PN junction is increased with higher doping levels. Thus, the carrier injection is concentrated underneath the collector region N/+/6 resulting in an increased inverse current gain.

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