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Test for FET Gate Stability

IP.com Disclosure Number: IPCOM000073985D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR [+2]

Abstract

This method presents a quick test for gate oxide stability of n-channel enhancement FET devices by determining the shape of the current recovery curve after applying a negative bias to the gate. The method eliminates the need for measuring the shift in flat band charge after a long period of high-temperature bias stress.

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Test for FET Gate Stability

This method presents a quick test for gate oxide stability of n-channel enhancement FET devices by determining the shape of the current recovery curve after applying a negative bias to the gate. The method eliminates the need for measuring the shift in flat band charge after a long period of high-temperature bias stress.

Normally fabricated n-channel FET's exhibit measurable drain current unless the substrate is biased. In the absence of a substrate bias, a large negative bias applied to the gate, will also reduce the drain current to zero. The rate of recovery of drain current after the bias is removed is an indication of the mobile charge, or charge-producing contaminants, in the gate oxide. If the time required to reach 1/e of the original current is plotted against 1/t on log paper, the slope of the curve is equal to the activation energy of the drift process and the particular impurity may be identified.

An ideal device should have a square recovery curve as shown by curve 1. In fact, an actual stable device exhibits an over-shoot as shown by curve 2 due to cooling of the channel during biasing. An unstable device will have a flatter recovery curve 3 due to excess charge in the gate oxide. Observation of the recovery curve after a short negative-gate bias pulse enables qualitative testing of devices in a minimum amount of time.

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