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Series N Channel MOSFET Gate Protection Circuit

IP.com Disclosure Number: IPCOM000073987D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Boss, CD: AUTHOR [+3]

Abstract

This circuit provides protection for the gate of FET 10 formed on a monolithic chip while the chip is not being used, but permits signals to reach the gate when the chip is properly energized. When an electrostatic discharge causes a high voltage to be applied between terminal G IN and the substrate terminal 18 while terminal VH is not connected to any supply voltage, the gated diode 12 will limit the input voltage to device 14 to approximately 60V. Capacitors C1 and C2 are chosen to act as a capacitive voltage divider that restricts the voltage across the oxide gate of device 14 to something which is less than that which is destructive. This turns on device 14 so that its source terminal can rise no higher than one threshold voltage drop below its gate potential.

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Series N Channel MOSFET Gate Protection Circuit

This circuit provides protection for the gate of FET 10 formed on a monolithic chip while the chip is not being used, but permits signals to reach the gate when the chip is properly energized. When an electrostatic discharge causes a high voltage to be applied between terminal G IN and the substrate terminal 18 while terminal VH is not connected to any supply voltage, the gated diode 12 will limit the input voltage to device 14 to approximately 60V. Capacitors C1 and C2 are chosen to act as a capacitive voltage divider that restricts the voltage across the oxide gate of device 14 to something which is less than that which is destructive. This turns on device 14 so that its source terminal can rise no higher than one threshold voltage drop below its gate potential. Therefore, the voltage at G OUT is also nondestructive, and will not destroy the gate of device 10.

When the chip is module and card mounted, terminal VH is connected to the highest available positive source. This turns on device 16 which DC biases the gate of device 14 to one threshold voltage drop below VH. Capacitors C1 and C2 then provide positive feedback to device 14 to reduce the input response degradation introduced by device 14.

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