Browse Prior Art Database

High Speed Transistor

IP.com Disclosure Number: IPCOM000073999D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Ashar, KG: AUTHOR

Abstract

This device has a low-collector capacitance, low-collector resistance, and higher-current density handling capability.

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High Speed Transistor

This device has a low-collector capacitance, low-collector resistance, and higher-current density handling capability.

Conventional integrated circuit semiconductor transistors are fabricated by diffusing in a monocrystalline semiconductor body base region, followed by a subsequent diffusion which produces an emitter region within the original base region. When the transistor is used in high-speed operation the collector impurity concentration is critical. If it is too high the base to collector capacitance is high, and if it is too low the collector resistance is high. Any attempt to reduce collector capacitance by reduced collector doping at base-collector junction results in base stretching or "Kirk effect" which makes cutoff frequency fall at high currents.

The structure, shown in C, achieves a low-collector capacitance and a low- collector resistance by utilizing a pushed-out portion in the bottom of the base region which occupies only a small portion of the area of the base. This limits the capacitance. Since the capacitance is decreased the impurity concentration at the collector-base interface can be increased thus providing a low-collector resistance.

The method for producing the structure is shown in A, B, and C.

A P- wafer 10, having a subcollector region 12 and an N- epitaxial layer 14, is covered with a thermal oxide layer 16. An opening 18 is formed overlying the intended emitter region and the device subjected to further therm...