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Optimum and Symmetrical Error Correction Code

IP.com Disclosure Number: IPCOM000074001D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Dobrzynski, SM: AUTHOR

Abstract

This code can be implemented with less hardware than other existing codes to permit single-error correction and double-error detection.

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Optimum and Symmetrical Error Correction Code

This code can be implemented with less hardware than other existing codes to permit single-error correction and double-error detection.

The code is truly symmetrical. That is, the code for bits 32 to 64 is identical to that for bits 1 to 32, except that it is rotated by 180 degrees. The matrix is so organized so as to make optimum use of the four-way or two-way Exclusive OR. Parity checks can be generated in two logic level check bits and two syndrome bits.

Error detection and correction can be done by adding three more logic levels for a total of seven logic levels through the system.

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