Browse Prior Art Database

Adaptive Majority Logic

IP.com Disclosure Number: IPCOM000074002D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR [+2]

Abstract

The system is designed for single and double-error correction. The basic requirement of the Adaptive Majority Logic (AML) system is to design a 2-out-of-3 voter and then extend it to a 3-out-of-5 voter. During the extension process, the original design of the 2-out-of-3 voter will not be changed. Therefore; if a logic system has triple modular redundancy and uses a single system for single-error correction, it can be extended to double-error correction by adding two extra copies of redundancy and an additional system circuit, as shown in A.

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Adaptive Majority Logic

The system is designed for single and double-error correction. The basic requirement of the Adaptive Majority Logic (AML) system is to design a 2-out-of-3 voter and then extend it to a 3-out-of-5 voter. During the extension process, the original design of the 2-out-of-3 voter will not be changed. Therefore; if a logic system has triple modular redundancy and uses a single system for single-error correction, it can be extended to double-error correction by adding two extra copies of redundancy and an additional system circuit, as shown in A.

When it is used for single-error correction, the only output line used is a(1). a(1) = Maj [A(1), B(1), C(1)]. In the case of double-error correction, two circuits are used and connected. Note that the output F is given as follows: F = Maj [A(1), B(1), C(1), A(2), B(2)].

The system contains two basic circuits. The first 2-out-of-3 circuit with the outputs a(1), b(1) and c(1) have the following logic functions respectively: a(1) = A(1)B(1)+B(1)C(1)+C(1)A(1) (1) b(1) = A(1)B(1)C(1) (2) c(1) = A(1)+B(1)+C(1) (3). Next, the 3-out-of-5 extension box is described as follows: a(2) = A(2)+B(2) (4) b(2) = A(2)B(2) (5) F = b(1)+a(1)a(2)+C(1)b(2) (6). It can be verified that F is the majority of the five input variables A(1),B(1),C(1),A(2) and B(2).

These voters can be implemented with known Read-Only Memory (ROM) arrays, as illustrated at B.

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