Browse Prior Art Database

Conducting Path for Power Distribution

IP.com Disclosure Number: IPCOM000074003D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ting, CH: AUTHOR

Abstract

In a complicated integrated circuit, the metallurgy can be simplified if power distribution to individual circuits is achieved by bringing in the power from the back of the semiconductor chip through a diffused channel. However, in certain packaging configurations there are no electrical connections on the backside of the chip and power has to be brought into backside of the chip by another diffused channel along the periphery of the chip, as shown in A. Since there is considerable amount of power to be distributed to each chip, the diffused channel along the periphery has to be of considerable size thus limiting the useful space of a given chip size.

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Conducting Path for Power Distribution

In a complicated integrated circuit, the metallurgy can be simplified if power distribution to individual circuits is achieved by bringing in the power from the back of the semiconductor chip through a diffused channel. However, in certain packaging configurations there are no electrical connections on the backside of the chip and power has to be brought into backside of the chip by another diffused channel along the periphery of the chip, as shown in A. Since there is considerable amount of power to be distributed to each chip, the diffused channel along the periphery has to be of considerable size thus limiting the useful space of a given chip size.

Drawing B illustrates a technique for connecting the power to the backside of the semiconductor chip without the diffused channel along the periphery, thus increasing the useful area of a given chip and simplifying the fabrication process. The configuration is obtained by plating the entire chip, except the front face, with metal, such as copper, nickel, silver, gold, etc. and connecting the plated metal surface to the power line by means of a solder joint or any other suitable method. The simplest plating process is by displacement plating or electroless plating. Since the electrochemical activity of silicon is high while that of SiO(2)is low, plating action occurs on all bare silicon surfaces, that is, the back and all sides of the silicon semiconductor, but not on the front...