Browse Prior Art Database

Test Structures for Ionic FETs

IP.com Disclosure Number: IPCOM000074009D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Evrenidis, P: AUTHOR [+3]

Abstract

Detection of the source of ionic FET's in MOS devices is simplified by these structures. The devices shown consist of a semiconductor substrate having electrodes 1 and 2 placed in various positions relative to dielectric covered diffusions 3 and 4. The dielectric thickness is the same as that thought to be causing parasitic ionic FET's in standard devices.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Test Structures for Ionic FETs

Detection of the source of ionic FET's in MOS devices is simplified by these structures. The devices shown consist of a semiconductor substrate having electrodes 1 and 2 placed in various positions relative to dielectric covered diffusions 3 and 4. The dielectric thickness is the same as that thought to be causing parasitic ionic FET's in standard devices.

The device shown in A allows the examination of the possibility that ions causing ionic FET operation are coming from the electrodes themselves. If the ions are coming from the electrodes, a difference in "turnon" time will be noted depending upon the polarity of electrodes 1 and 2 due to the differences in the distance between the edge of the electrode and the edge of the opposite diffusion.

The device shown in B incorporates an electrode 1 mounted over the substrate between diffusions 3 and 4 and allows the effect of ionic migration in the dielectric over the channel to be maximized. Comparison of the results of devices A and B having the same channel length will further aid in identifying the source of the undesirable ions. The device shown in C allows examination of ionic FET's for small geometries and for variations in channel width of the ionic FET's which may be caused by variations in time, temperature, voltage, etc., during temperature bias stress.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]