Browse Prior Art Database

Buffered Control Unit for a 96 Column Card

IP.com Disclosure Number: IPCOM000074026D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Kerr, JW: AUTHOR [+3]

Abstract

This control unit utilizes data from a reader which reads data in the character sequence columns 1, 33, 65, 2, 34, 66 etc., from the three tiers T1, T2, and T3 of a document card 8, as shown in A, and passes it on to a data processing system in the normal character sequence, columns 1, 2, 3. . .96.

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Buffered Control Unit for a 96 Column Card

This control unit utilizes data from a reader which reads data in the character sequence columns 1, 33, 65, 2, 34, 66 etc., from the three tiers T1, T2, and T3 of a document card 8, as shown in A, and passes it on to a data processing system in the normal character sequence, columns 1, 2, 3. . .96.

As shown in B, data is transferred from a read head 10 to read data converters 11 by bus 12 and is fed by buses 13, 14, and 15 to read data register
16. Buses 13, 14, and 15 respectively contain data read from tiers 1, 2, and 3 of card 8; and this data is also fed to read checking logic 17. The data in register 16 is fed through 3 to 1 assembly 18 into buffer 20. The data is held in buffer 20 for a time and flows through translate logic 22 into data bus in (DBI) register 24 to data bus in 26 by means of which it is transferred to the data processing system. Register 16 and assembly 18 are under the control of read control logic 28. Read control logic 28 as well as channel control logic 30 both control address control logic 32 which controls buffer 20 so that the data from assembly 18 flows to buffer 20 first for tier 1, then for tier 2, then for tier 3 for each of the aligned columns (columns 1, 33, 65, etc.) and flows out of buffer 20 serially, columns 1, 2, 3. . .96.

As shown in C, address control logic 32 includes a counter 34 and address select logic 35 which controls buffer 20. Counter 34 is used as a standard seven-position binary counter for a transfer of data from buffer 20 to DBI 26 with the data being transferred from buffer 20 in the normal character sequence 1, 2,
3. . .96; and in this case (channel data transfer mode), channel data transfer advance pulses 36 are obtained from channel control 30 and are effective on counter 34 through OR circuit 37. In this case, the pulses 36 will cause counter 34 to count in sequence 1, 2, 3. . .96 with counter 34 acting as a seven-position binary counter.

In the case in which data is transferred to buffer 20 (card read mode), card read mode advance pu...