Browse Prior Art Database

Automatic Loop Gain Regulation

IP.com Disclosure Number: IPCOM000074043D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Walach, AZ: AUTHOR

Abstract

A circuit is shown for reducing DC loop gain variation in phase controlled regulators. A typical phase controlled (3 phase primary) regulator is shown in A. It can be shown that the DC loop gain for the regulator is proportional to (tan Kt(f)) dt(f) over dV(t) where V(T) is the amplified DC error voltage and t(f) is the 'phaseback time', i.e., the time from the Time Reference to the time when the SCR's (silicon controlled rectifiers) are fired. The Time Reference is synchronized with the 3phi input voltage on the transformer primary winding. The SCR's triggering pulse is generated whenever the Timing Circuit output reaches V(T).

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Automatic Loop Gain Regulation

A circuit is shown for reducing DC loop gain variation in phase controlled regulators. A typical phase controlled (3 phase primary) regulator is shown in A. It can be shown that the DC loop gain for the regulator is proportional to (tan Kt(f)) dt(f) over dV(t) where V(T) is the amplified DC error voltage and t(f) is the 'phaseback time', i.e., the time from the Time Reference to the time when the SCR's (silicon controlled rectifiers) are fired. The Time Reference is synchronized with the 3phi input voltage on the transformer primary winding. The SCR's triggering pulse is generated whenever the Timing Circuit output reaches V(T).

t(f) varies with the load current and the magnitude of voltage at the choke input. The DC loop gain can vary as much as 10 to 1 from system to system. In order to reduce the DC loop gain changes with the operating t(f) the output of the Timing Circuit should be made proportional to the square of t(f). B illustrates a circuit (t/2/circuit) which accomplishes the desired result quite efficiently. Ideally (tan Kt(f) dt(f) over dV(t) should be constant for large changes in load current or voltage changes at the input to the filter. This requires that

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