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Digital Filter and Threshold Circuit

IP.com Disclosure Number: IPCOM000074048D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR

Abstract

The analog resistive weighting and summing network and delta demodulator normally associated with transversal type filters, may be replaced by a simplified logic circuit and a digital counter. The successively delta encoded binary signals are applied to an M-stage shift register (SR) 305. A logic arrangement, comprising AND gates 325, 327, 329 followed by OR circuits 347, 349, 351, dispatches the binary signals present at preselected M1, M2 and M3 stages of the SR 305, to preselected ones (depending on desired weights) of the stages of a binary counter accumulator 315. Clock and gating circuitry 321 control the gates 325, 327, 329 successively.

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Digital Filter and Threshold Circuit

The analog resistive weighting and summing network and delta demodulator normally associated with transversal type filters, may be replaced by a simplified logic circuit and a digital counter. The successively delta encoded binary signals are applied to an M-stage shift register (SR) 305. A logic arrangement, comprising AND gates 325, 327, 329 followed by OR circuits 347, 349, 351, dispatches the binary signals present at preselected M1, M2 and M3 stages of the SR 305, to preselected ones (depending on desired weights) of the stages of a binary counter accumulator 315. Clock and gating circuitry 321 control the gates 325, 327, 329 successively. During a delta sampling time interval T, each of the AND gates may be individually turned on, so as to gate the signal contents of the corresponding SR stage through the appropriate counter stages. Accordingly, during each shift time, the contents of SR 305 at each stage are weighted and summed. For instance if all three stages M1, M2, M3 contained a binary one, then decimal value fourteen would be added to counter 315. The highest-order bit of the counter then serves as the output of the filter.

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