Browse Prior Art Database

Clock Timing and Permutation

IP.com Disclosure Number: IPCOM000074055D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Davis, WH: AUTHOR [+2]

Abstract

In sequential processors having an instruction time of fixed duration, such as eight word times, the processing speed can be increased by a clock permutation technique which effectively allows skipping of processing cycles.

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Clock Timing and Permutation

In sequential processors having an instruction time of fixed duration, such as eight word times, the processing speed can be increased by a clock permutation technique which effectively allows skipping of processing cycles.

As illustrated in A the normal processing sequence is RWA, RWB, RWC and RWD which are determined by combinations of the logical signals shown. SSA determines the duration of the cycles and SSB is not used. The particular tasks assigned to the clock times RWA, RWB, RWC, and RWD are initiated by the SSA pulse occurring in middle of each such time, and are finished before the second SSB pulse occurs to provide separation time between cycles to allow transients to die down.

As illustrated in B, permutation from RWB to RWD can be accomplished by crowding RWC into the separation time which occurs during the last quarter of RWB by resetting T(1) with the combination of T(2).C(1).SSB after the normal reset of TS by T(1).T(2).C(2).SSA has been inhibited. In essence then, in the permutation mode, the normal beginning and ending of cycles does not always occur with SSA, but instead some cycles begin with SSA and end with SSB by substituting SSB as a logical term of the required previous logical condition and inhibiting resetting of T(s).

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