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Shifter Design Using Partitioned Arrays

IP.com Disclosure Number: IPCOM000074058D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 97K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

This shifting-code permits the shifting of a 16-bit word any number of positions right or left.

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Shifter Design Using Partitioned Arrays

This shifting-code permits the shifting of a 16-bit word any number of positions right or left.

An article appearing in the June 1970 issue of "Computer Design" magazine describes the structuring of logic arrays on monolithic chips 10 with a degree of regularity comparable with that of a memory. The inputs to the chips 10 are through partitioned decoders 12a to 12d to a matrix 14 of AND circuits which receive one input from the decoder and a second input from a memory which determines the logic functions or subfunctions generated by the chip.

With such chips a single-level shifting circuit that will shift a 16-bit input up to sixteen positions in either direction can be generated using a 5-bit code. The connections to the chips are included in the drawing where D1 through D16 are the input data, C1 through C5 the shift code, and SD1 through SD16 the shifted output data. The first four positions C1 through C4 of the code indicate the number of positions the data is to be shifted left while the fifth position C5 tells whether or not the data is to be shifted right 16 positions. The code and the relationship between inputs and outputs are outlined in the table B. The logic formula for the output SD1 is also shown at C. The logic formulas for the other outputs SD2 through SD16 follow accordingly.

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