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Digital Comparison within a Tolerance

IP.com Disclosure Number: IPCOM000074089D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

McCarthy, CE: AUTHOR

Abstract

Binary number properties can be used to advantage with the following algorithm to implement a digital comparator which can compare two binary numbers and indicate when they are not within a prescribed binary tolerance. The prescribed binary tolerance is defined as equal in value to the value of the lowest-order binary bit. The Algorithm includes the following three steps:

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Digital Comparison within a Tolerance

Binary number properties can be used to advantage with the following algorithm to implement a digital comparator which can compare two binary numbers and indicate when they are not within a prescribed binary tolerance. The prescribed binary tolerance is defined as equal in value to the value of the lowest-order binary bit. The Algorithm includes the following three steps:

1) Determining a mark bit position which is the highest-order bit position of disagreement between two binary numbers being compared.

2) Determining which of the two numbers being compared is the larger number (when they differ).

3) Determining that the numbers compare within the prescribed binary tolerance when they differ, if:

(a) the larger of the two numbers has a 1 in the mark bit position and 0's in all lower-order bit positions within the prescribed binary tolerance; and,

(b) the smaller of the two numbers has a 0 in the mark bit position and has all 1's in each lower-order bit position within the prescribed binary tolerance.

Drawing A shows a four-bit word length parallel comparator capable of comparing word X with word Y and detecting a noncompare within a one-bit binary tolerance. Exclusive-OR circuits 11, 12, and 13 compare the higher-order bit positions to locate the mark bit position. The AND circuits 14, 15, 16, 17, 18 and 19 determine which of the two words being compared is the larger word. Only that particular AND gate of AND gates 14 through 19 corresponding to the larger word mark bit position will be conditioned. Having identified the mark bit position and which of the words X or Y is the larger word, OR gates 21 through 26 and AND gates 31 through 36 logically determine whether the lower-order bit values of the larger word are 0's.

Inverters 41 and 42 determine that the lowest-order bit value of the smaller word is a 1.

Inverters 43, 44, and 45 verify that there is a noncompare in all higher-order bit positions, thus verifying that the mark bit position of the smaller word is a 0 and intermediate bits (2 and 4 in this case) are 1's.

The OR gate 46 provides-an output at 47 whenever a noncompare within a binary tolerance is detected.

Drawing B shows a serial comparator capable of comparing a word X of any length, with another word Y of equal length. The words X and Y are serially transmitted to the inputs of Exclusive-OR 51 in high to lower-order bit sequence. That is the highest-order bits appear first. Exclusive-OR circuit 51, first provides an output at the highest-order bit position of disagreement between the two binary numbers being compared, there...