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Selective Length Redundancy Coding Register

IP.com Disclosure Number: IPCOM000074129D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Chien, RT: AUTHOR [+3]

Abstract

In data transmission systems where the block length of data varies, efficiency is improved by corresponding changes in the amount of redundancy added for error control. In short blocks, sufficient protection may be obtained by sending less redundancy than is needed on long blocks and where many short blocks are sent, such as in polling sequences, line efficiency may be substantially increased.

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Selective Length Redundancy Coding Register

In data transmission systems where the block length of data varies, efficiency is improved by corresponding changes in the amount of redundancy added for error control. In short blocks, sufficient protection may be obtained by sending less redundancy than is needed on long blocks and where many short blocks are sent, such as in polling sequences, line efficiency may be substantially increased.

In the drawing, a full length 16-bit shift register is used to detect and correct errors in long data blocks and this register can be shortened and changed to a different feedback configuration for short block lengths. The register comprises register orders 1 through 16 connected in series with Exclusive OR (XOR) circuits 17 through 23 between each of 1 through 8 and circuits 24, 25, and 26 being connected between orders 10 and 11, 13 and 14, and 15 and 16, respectively.

Two control signals are used to set the shift register for its different operations. An S signal is present when the register is used as a 16-bit checker and is absent when the shift register is to be restricted to eight bits. A D signal is used to shift from an error correcting configuration when the D signal is present to an error checking configuration when the signal is not present. With neither signal present, the configuration is an eight-bit error checker using a premultiplication factor of X to the second, fourth, and sixth powers. An input signal on line 30 is passed through AND 31 by the not D signal complemented in inverter 32 to a line 33. The line 33 input is passed through AND 34 by the not S signal complemented in inverter 35 and is entered into XOR 36 feeding XOR 20, and through OR 37 to XOR 38 feeding XOR 18 and to XOR 22 thus providing the required premultiplication. The output of stage 8 is passed through AND 39 by the not S signal complemented in inverter 40 and through OR 41 to enter stage 1 input and XOR's 17, 38, 36 and 23.

When the S signal is present, the registers function in a 16-bit configuration. The input signal on line 33 now is passed through AND 42 by the S signal to enter XOR's 19, 21, and 24, and through OR 37 to XOR's 38 and 22 giving a premultiplication by a factor of X to the second, third, fifth, sixth, and tenth powers. Stage 8 connects to stage 9 through AND 60 and the output of stage 16 is passed through AND 43 by the S signal to a line 44 for entry into XOR's 26 and 25 and throu...