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Digital Receiver Circuit

IP.com Disclosure Number: IPCOM000074134D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Bell, DJ: AUTHOR [+4]

Abstract

A digital receiver circuit with high-dynamic input impedance comprises a PNP transistor Q1 with a collector input and an emitter connection to the base of an NPN transistor Q2. The voltage level of the base of transistor Q1 is set by resistors R1 and R2, connected to voltage sources V1 and V2.

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Digital Receiver Circuit

A digital receiver circuit with high-dynamic input impedance comprises a PNP transistor Q1 with a collector input and an emitter connection to the base of an NPN transistor Q2. The voltage level of the base of transistor Q1 is set by resistors R1 and R2, connected to voltage sources V1 and V2.

An input signal with a voltage level less than the voltage at the base of transistor Q1 linearly biases Q1 and turns transistor Q2 off. An input signal with a voltage above the bias voltage at the base of transistor Q1 allows current through resistor R3 to raise the voltage at the base of transistor Q1 thereby turning on- transistor Q2. The collector of transistor Q1 for input down levels and reversed bias diode D1 for input up levels maintains a high-bipolar input impedance over a large-input voltage range.

The threshold can be varied by changing the PNP transistor quiescent point and/or by placing a resistor or zener diode in the base circuit of transistor Q2.

Suitable components for use in the circuit are listed as follows: R1 32K ohms V1 +15 volts D1 FD100 R2 28K ohms V2 -15 volts Q1 2N2907 R3 5K ohms V3 + 5 volts Q2 2N709 R4 4K ohms.

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