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Demodulator

IP.com Disclosure Number: IPCOM000074138D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Dix, GL: AUTHOR

Abstract

A double frequency data signal is demodulated to separate the clock signals from the data signals. The double frequency modulated data signal is applied to inverter 10, negative clock flip-flop 15 and AND circuit 30. The output of 10 is applied to switch positive clock flip-flop 20. Flip-flops 15 and 20 are set by a negative transition. Their reset outputs are applied to OR circuit 35. The output of 35 is applied to inverter 40 and count gate flip-flop 50. The output of 40 conditions 15 and 20. Flip-flop 50 is set by a positive transition of a pulse from oscillator 70. The output of 50 resets counter 55 which is being advanced by pulses from 70. When counter 55 reaches a particular count as determined by AND circuit 60, flip-flops 15 and 20 are reset.

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Demodulator

A double frequency data signal is demodulated to separate the clock signals from the data signals. The double frequency modulated data signal is applied to inverter 10, negative clock flip-flop 15 and AND circuit 30. The output of 10 is applied to switch positive clock flip-flop 20. Flip-flops 15 and 20 are set by a negative transition. Their reset outputs are applied to OR circuit 35. The output of 35 is applied to inverter 40 and count gate flip-flop 50. The output of 40 conditions 15 and 20. Flip-flop 50 is set by a positive transition of a pulse from oscillator 70. The output of 50 resets counter 55 which is being advanced by pulses from 70. When counter 55 reaches a particular count as determined by AND circuit 60, flip-flops 15 and 20 are reset. This also causes 50 to reset on the next positive transition of oscillator 70. If the double frequency encoded data signal is at a positive level while flip-flop 15 is set, then the conditions of AND circuit 30 are satisfied and data detect flip-flop 65 will be conditioned for being set by OR circuit 45. Under this condition, 65 is set when an output from 40 goes positive. Flip-flop 65 will also be conditioned for setting when the inputs to AND circuit 25 are satisfied. This occurs when the double frequency encoded data signal is at a negative level and flip-flop 20 has been set.

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