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Interrupt and I/O Operations Handling

IP.com Disclosure Number: IPCOM000074173D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Lum, J: AUTHOR

Abstract

Improved performance and core efficiency can be obtained for handling interrupt and I/O operations by redefining the load PSW and the start, halt and test I/O machine instructions. These are the SI type instructions in which the immediate operand field is usually zeroed for IBM System/360 and 370 operations. In the redefined instructions, use is made of the immediate operand field to pass information to the hardware.

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Interrupt and I/O Operations Handling

Improved performance and core efficiency can be obtained for handling interrupt and I/O operations by redefining the load PSW and the start, halt and test I/O machine instructions. These are the SI type instructions in which the immediate operand field is usually zeroed for IBM System/360 and 370 operations. In the redefined instructions, use is made of the immediate operand field to pass information to the hardware.

By way of example, the load PSW instruction can be redefined as follows: LPSW D1 (B1), R2, R3. With this instruction, LPSW is the mnemonic, D1 (B1) specifies the displacement and base register of a core location (PSWLOC) in which the pSW is to be stored, and R2 and R3 specify nonzero general purpose registers which respectfully contain the addresses of storage locations at which the interrupt code will be located and where the general purpose registers will be stored. These locations are known as the CODELOC and the CPRLOC.

Referencing flow chart B, when the LPSW instruction is issued, the first 4 bits of the immediate operand field are checked for specification of a nonzero general purpose register. If a valid register is specified, its contents are then checked for a valid address and the contents of the GPR's are stored at the CODELOC. Then the R3 field is checked. When a register is properly specified, the register contents are first checked and then the GPR contents are stored at the GPRLOC. Thereafter, the GPR's are loaded by the current program. The next step involves using the PSW address to develop the PSW location. This step and subsequent steps are common regardless of whether or not the immediate operand field is zeroed. PSW is then checked for errors and it is stored at the PSW location. The R2 and R3 fields are placed on...