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IGFET Functional Memory Cells

IP.com Disclosure Number: IPCOM000074185D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Dailey, JR: AUTHOR [+2]

Abstract

Functional memory storage cells 20 store the four states 10, 01, 00 and 11 of two bits B0 and B1 of binary information.

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IGFET Functional Memory Cells

Functional memory storage cells 20 store the four states 10, 01, 00 and 11 of two bits B0 and B1 of binary information.

At A, cell 20 has two identical stages 21 and 22 which store the two bits B0 and B1, respectively. Each stage has two parallel branches 23 and 24. Branch 23 has a pair of series connected complementary P-channel and N-channel Insulated Cate Field-Effect Transistors (IGFET's) 25 and 26 which operate in a complementary manner to provide a low-power drain. IGFET 26 stores the particular binary bit with which the particular stage is associated. The other branch, 24 also has a pair of series connected P-channel and N-channel IGFET's 27 and 28, which also are operated in a complementary manner to provide a low- power drain. The two branches 23 and 24 of a stage also act in a complementary manner with respect to each other, the particular branch 24 latching the other branch 23 of the stage. The source, drain and gate electrodes of the various IGFET's are identified by the reference characters S, D, and G, respectively. Each stage also has a WRITE ENABLE gate 29 and READ OUT gate 30, which are implemented as N-channel IGFET's.

The cell uses only four signal lines, to wit, a common WRITE ENABLE line 31, two bit lines B0 and B1 associated with stages 21 and 22, respectively, and a common WORD line 32. The cell uses a single power supply, not shown, which applies a bias level VDD at common bus line 33. In practice, cell 20 is connected to other identical cells, not shown, of a functional memory storage array.

The cell operates in search/select, read, and/or write modes. The various bit lines B0, B1 and the states of IGFET's 26, 28, 30 of stages 21 and 22 for the various cell states are shown in TABLE 1.

In the search/select operational mode, the desired binary levels are applied to the B0 and B1 bit lines and all array cells connected to these bit lines are interrogated simultaneously. During this mode,...