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Browse Prior Art Database

Dynamic Shift Register With Static Storage

IP.com Disclosure Number: IPCOM000074190D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

The PNPN devices used in this shift register cell 10 operate as transistors to shift the data through the cell 10 and as SCR's to statically store the data in the cells.

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Dynamic Shift Register With Static Storage

The PNPN devices used in this shift register cell 10 operate as transistors to shift the data through the cell 10 and as SCR's to statically store the data in the cells.

The schematic shows the two stages of one of the cells 10 in a shift register. After a signal appears at the input 12 of the cell the potential at the terminal 14 is raised. If a "1" is at the input, the NPN portion of PNPN device 16 conducts causing the capacitor 18 to be held discharged. If a "0" is at the input at this time, the NPN transistor portion of the PNPN device 16 is held nonconducting so that the capacitor 18 is charged from the terminal 14.

The charge on capacitor 18 now serves as the input to the PNPN device 20 in the second stage and the cycle is repeated. This time terminal 22 is raised and the data placed on the capacitor 24 depends on whether capacitor 18 is or is not charged. If capacitor 18 is charged, capacitor 24 is maintained discharged by the conduction of the NPN transistor portion of device 20. While if capacitor 18 is discharged capacitor 24 is charged from terminal 22. Therefore, the data on capacitor 24 is exactly the same as the data to the input terminal 12 to the cell since two inversions of the data occur, one at each of the two stages of the cell.

Once all the data has been shifted into the proper position in the shift register the data stored there can be fixed in position by raising the potential across the devices 16...