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Browse Prior Art Database

MOS FET Storage Cell

IP.com Disclosure Number: IPCOM000074206D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+3]

Abstract

The bistable storage cell consists of two cross-coupled cell FET's T1 and T2 whose respective load branches comprise one load FET TS or T6 each. The coupling points are connected to associated bit lines BL1 and BL2, via one of the write-read FET's T3 or T4 whose gates are controlled via word line WL. The information is stored as a load difference in the capacities associated with the coupling points.

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MOS FET Storage Cell

The bistable storage cell consists of two cross-coupled cell FET's T1 and T2 whose respective load branches comprise one load FET TS or T6 each. The coupling points are connected to associated bit lines BL1 and BL2, via one of the write-read FET's T3 or T4 whose gates are controlled via word line WL. The information is stored as a load difference in the capacities associated with the coupling points.

To maintain the stored information, the leakage current losses discharging these capacities are compensated for via high-resistivity load FET's T5 and T6. To this and, the load FET's (in the case of n-channel FET's) are linked with positively biased bit lines BL1 and BL2. The gates of the two load FET's T5 and T6 are also linked with the associated bit lines BL1 and BL2 or are connected to a common bias V.

During reading, load FET's T5 and T6 are bridged by write-read FET's T3 and T4 which are rendered conductive via word line WL. The supply of the standby charge thus remains unaffected. During writing, the associated write- read FET's T3 and T4 are made conductive via word line WL, bridging load FET's TS and T6, and one of the bit lines BL1 or BL2 is reduced to ground potential. The supply of the standby charge to the selected cell is not affected in this case either.

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