Browse Prior Art Database

Programmable Character Generator

IP.com Disclosure Number: IPCOM000074224D
Original Publication Date: 1971-Mar-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Holderness, CJ: AUTHOR

Abstract

High speed read-only storage devices have been used for alphanumeric character generators. These devices do not have the flexibility to operate in situations where a change of character sets is required, such as, in the area of character graphics.

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Programmable Character Generator

High speed read-only storage devices have been used for alphanumeric character generators. These devices do not have the flexibility to operate in situations where a change of character sets is required, such as, in the area of character graphics.

A low speed, changeable, read-only storage device is utilized to store all segments of all characters to be displayed. Segments of the characters to be displayed are read from ROS device into a read/write storage device which is used for generating the actual character segments.

The basic character generator shown contains segment generators 17 and
18. These are read/write storage devices. These read/write storage devices 17, 18 are addressed through address decodes 11, 12 and 13 under the control of address switches 15, 16. Address decoders 11, 12 and 13 convert the character code to an address in one of the segment generators 17 or 18 for that character segment.

Character data is written into segment generators 17 and 18 from transformer read-only storage 19 under the control of TROS address and control unit 14 when address decoder 13 is gated through one of switches 15, 16 to segment generators 17 or 18. Characters are generated for four channels concurrently by parallel operation in segment generators 17 and 18. A character code is read into address decoder 11 or 12. The output of which is an address required for segment generators 17 or 18.

Assume that segment generator 17 holds the first segment of all characters in a set. The character code for the first character of a first display is presented to address decoder 11. The address is then gated through switch 15 to segment generator 17 which provides the first segment of that character to display multiplex logic, not shown.

Next, the first character of a second display would be presented through address decoder 12, gated through switch 15 to segm...