Browse Prior Art Database

Decode Checking to Detect Failures in Transmission

IP.com Disclosure Number: IPCOM000074227D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR

Abstract

This checking scheme is applicable to a decoder in which the inputs to the decoder are accompanied by a parity bit. Presently, a parity network is provided to check the transmission of inputs to the decoder, or to check the contents of an address register. The present arrangement eliminates the need for the parity network, and makes use of a network for checking the decoder itself. Thus, by modifying the decoder checking network, the transmission and the decoder itself can be checked with the addition of very little hardware.

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Decode Checking to Detect Failures in Transmission

This checking scheme is applicable to a decoder in which the inputs to the decoder are accompanied by a parity bit. Presently, a parity network is provided to check the transmission of inputs to the decoder, or to check the contents of an address register. The present arrangement eliminates the need for the parity network, and makes use of a network for checking the decoder itself. Thus, by modifying the decoder checking network, the transmission and the decoder itself can be checked with the addition of very little hardware.

There are several types of single hardware failure errors which cannot be detected by the decoder checker, even though they may be considered to be a failure in transmitting one of the n inputs to the decoder. One such type failure arises where the first level of the decoder consists of phase splitters or latches, and the failure occurs in an input transistor of the phase splitter. The effect would be that of interchanging the X and Q outputs for that particular input. If a parity bit is available with the n inputs, then a slight modification of the decoder checker is capable of detecting this failure. Referring to diagram A, there is shown a decoder checker. When the parity of the n bits is even, line 1 should be positive; when the parity is odd, line 2 should be positive. Furthermore, if the decoder output is incorrect due to a transmission failure, then the signals on lines 1 and 2 will a...