Browse Prior Art Database

Addressing Method for Remote Television Buffers

IP.com Disclosure Number: IPCOM000074258D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Lawrence, G: AUTHOR [+5]

Abstract

This technique relates to addressing remote television buffers. It enables the addressing of one of a plurality of buffers when all of the buffers are on the same channel and provides an economical addressing technique for a low-cost video buffer. When a frame of information is intended for a remote buffer by a transmitting source, the addressing information, in the form of digital signaling (i.e., pulses) is added to some part or parts of the video signal by the source. The source, for example, may be a CPU controlled address generator. As shown, these address bits occur at a fixed time reference from the horizontal sync pulses. Horizontal lines 7 through 15 of the field do not contain any video or test signals and the address bits are placed on these lines. Line 1 occurs at the beginning of the vertical interval.

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Addressing Method for Remote Television Buffers

This technique relates to addressing remote television buffers. It enables the addressing of one of a plurality of buffers when all of the buffers are on the same channel and provides an economical addressing technique for a low-cost video buffer. When a frame of information is intended for a remote buffer by a transmitting source, the addressing information, in the form of digital signaling
(i.e., pulses) is added to some part or parts of the video signal by the source. The source, for example, may be a CPU controlled address generator. As shown, these address bits occur at a fixed time reference from the horizontal sync pulses. Horizontal lines 7 through 15 of the field do not contain any video or test signals and the address bits are placed on these lines. Line 1 occurs at the beginning of the vertical interval.

Address recognition in the intended buffer may be achieved by a shift register and a decode AND circuit in the receiving logic of the buffer. Both the vertical and horizontal sync pulse of the incoming video signal are utilized by suitable decode logic of the buffer. Line 7 of the field is preceded by the vertical sync pulse which is derived by a sync separator with the proper RC time constants. This vertical sync pulse is employed to reset the shift register. Each horizontal sync pulse following the vertical sync pulse may be employed to drive a circuit such as a monostable multivibrator which times at t...