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Fabrication of Field Effect Transistors

IP.com Disclosure Number: IPCOM000074274D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Zirinsky, S: AUTHOR

Abstract

In the fabrication or field-effect transistors, source and drain regions are diffused into a semiconductor substrate via openings in a silicon dioxide layer. Once these regions are formed, a gate region which extends between the source and drain diffusions must be provided which includes a thin-gate oxide and gate metallization. The field-effect transistor fabrication in accordance with the present teaching is carried out as indicated above. At this point, the above mentioned gate region is opened by well-known photolithographic and etching techniques and silicon is evaporated under the following conditions: (1) radio frequency source heating using an amorphous (glassy) carbon crucible containing boron doped high purity silicon as an evaporant source.

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Fabrication of Field Effect Transistors

In the fabrication or field-effect transistors, source and drain regions are diffused into a semiconductor substrate via openings in a silicon dioxide layer. Once these regions are formed, a gate region which extends between the source and drain diffusions must be provided which includes a thin-gate oxide and gate metallization. The field-effect transistor fabrication in accordance with the present teaching is carried out as indicated above. At this point, the above mentioned gate region is opened by well-known photolithographic and etching techniques and silicon is evaporated under the following conditions: (1) radio frequency source heating using an amorphous (glassy) carbon crucible containing boron doped high purity silicon as an evaporant source. (2) Evaporation rate under 5 Angstroms/second within a vacuum of 10/-6/ Torr or better (previously evacuated and backfilled with oxygen) and substrate temperature between room temperature and 100 degrees C.

The deposited silicon film is etched removed outside of the gate regions, source and drain contact via holes are opened and chromium (500 - 1000 Angstroms) plus copper (50 Angstroms) plus aluminum (5000 - 9000 Angstroms) deposited for source, drain, and gate electrodes.

The use of amorphous silicon as the gate insulation has proved to be particularly advantageous with F-channel devices. After the metallization has been accomplished, further processing is exactly the same as...