Browse Prior Art Database

Storage Operation Sequence Detection

IP.com Disclosure Number: IPCOM000074282D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Granito, GD: AUTHOR

Abstract

There may be a variety of reasons for the necessity to be able to detect a specific sequence of buffer (or other storage) operations which reference a portion of the buffer. For example, this situation may arise if the relative speeds of the CPU and the buffer are such that the CPU may issue certain sequences of buffer accessing instructions at a faster rate than they may be executed.

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Storage Operation Sequence Detection

There may be a variety of reasons for the necessity to be able to detect a specific sequence of buffer (or other storage) operations which reference a portion of the buffer. For example, this situation may arise if the relative speeds of the CPU and the buffer are such that the CPU may issue certain sequences of buffer accessing instructions at a faster rate than they may be executed.

Given a system where it is undesirable to attempt to access the same quadrant of a basic storage module BSM with a FETCH operation which immediately follows a STORE operation, this undesirable sequence can be detected through the use of two AND circuits A1 and A2 and a compare circuit C. A1 is fed by two inputs which indicate that the instruction of the previous CPU cycle included a STORE operation and that the instruction of this cycle includes a FETCH operation, and the inputs to C are the storage address referenced by the previous cycle and the storage address referenced by this cycle. C will compare those portions of the two addresses which determine the referenced quadrant of a BSM. When an output is generated by Al (indicating that the sequence STORE-FETCH occurred on successive CPU cycles) and an output is generated by C (indicating that both of the buffer accessing instructions were to the same quadrant of the same BSM) an output will be generated by A2. This output will be used to inhibit the FETCH operation for one cycle (or longer if n...