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Browse Prior Art Database

Elimination of Ionic FET's

IP.com Disclosure Number: IPCOM000074328D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Evrenidis, PE: AUTHOR [+2]

Abstract

This structure provides reduced parasitic transistor action between MOSFET devices by trapping ionic contaminants with substrate grounded metallic guard electrodes.

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Elimination of Ionic FET's

This structure provides reduced parasitic transistor action between MOSFET devices by trapping ionic contaminants with substrate grounded metallic guard electrodes.

The MOSFET device consists of source 1 and drain 2 separated by thin oxide covered channel 3. Metal gate 4 completes the device. Adjacent to channel 3 are two metal guard electrodes 5 and 6 extending from source 1 to drain 2 and contacting substrate 7. For n-channel devices utilizing negatively biased substrate, electrodes 5 and 6 become negatively biased and prevent inversion due to positive ionic charges at the oxide-substrate interface, thereby preventing the formation of parasitic devices between adjacent MOSFET's.

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