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Sense Amplifier Latch

IP.com Disclosure Number: IPCOM000074338D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Batheret, PH: AUTHOR [+2]

Abstract

This sense amplifier latch comprises: a differential stage, T1, T2 which insures sense operation by comparing the input voltage E1 with the reference voltage VreF; a current generator T3, T4 which feeds the differential stage; a second differential stage T5, T6 which operates as a squarer and insures voltage amplification and inversion (R5 is large enough to act as a current generator); an OR circuit D3, D4, D5 which provides the reset input; an output stage 17; and a feedback path D1 which latches the circuit on the output.

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Sense Amplifier Latch

This sense amplifier latch comprises: a differential stage, T1, T2 which insures sense operation by comparing the input voltage E1 with the reference voltage VreF; a current generator T3, T4 which feeds the differential stage; a second differential stage T5, T6 which operates as a squarer and insures voltage amplification and inversion (R5 is large enough to act as a current generator); an OR circuit D3, D4, D5 which provides the reset input; an output stage 17; and a feedback path D1 which latches the circuit on the output.

The delay introduced by the first differential stage is small. Although the voltage excursion of the second stage is much greater than the first one, the delay involved by T5, T6 remains as small as the previous one. Transistor T5 of the second stage is preconditioned to become less or more conductive (depending on the input level), by connecting its collector to the collector of T2. Moreover, the diode D2 prevents the collector of T5 from dropping below a reference voltage, so that the Miller's effect is reduced to minimum. This circuit is sensitive to a current variation as low as 0.6mA and operates in less than 30 nanoseconds. It is useful for reading out information stored in a monolithic memory.

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