Browse Prior Art Database

Address Translation Method

IP.com Disclosure Number: IPCOM000074371D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Geller, A: AUTHOR

Abstract

In a high-speed digital processing unit, it is often desirable to have an address translation feature to facilitate the handling of programs within the storage system. As a consequence, certain program instructions generate logical addresses which must be translated into real addresses prior to the transmission of the address information to the storage unit.

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Address Translation Method

In a high-speed digital processing unit, it is often desirable to have an address translation feature to facilitate the handling of programs within the storage system. As a consequence, certain program instructions generate logical addresses which must be translated into real addresses prior to the transmission of the address information to the storage unit.

There are three principal sources of logic addresses. The first principal source is the logical address formed within the adder of the computer system which will normally represent the sum of the program base, plus the displacement to generate a given logical address. A second major source is the new instruction counter value which results from the loading of a new Program Status Word (PSW). A third source of logical addresses is from an instruction counter update or from data accesses such as for VFL operations.

In order to translate a logical address into a real address, it is normally necessary to do a number of table look-up operations in order to form from the logical address the real address. Because a number of fetches are required, the address translation process itself can be quite time consuming. In order to alleviate this timing problem, it is useful to provide certain apparatus which will make it unnecessary to translate addresses every time a storage location is fetched. This is accomplished by an associative array which is schematically shown. The associative array has N entries and for most purposes 16 entries might be sufficient. The associative array would be searched in order to determine if the index (X) field and the base (B) field for the given instruction are contained within one of the entries within the associative array. The requestor would contain an X field, a B field and an identification bit. These bits would be compared with the X field, the B field and the identification hit within the associative array. If all of these bits compare equal and if a valid bit is on within the associative array entry, signal is generated which would gate the real address from the given entry to the storage access unit. A final check would...