Browse Prior Art Database

Digital Frequency Discriminator

IP.com Disclosure Number: IPCOM000074378D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR

Abstract

This circuit provides for discrimination between signals of two different frequencies and is particularly useful for detecting frequency shift keying signals sent over a public switched network.

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Digital Frequency Discriminator

This circuit provides for discrimination between signals of two different frequencies and is particularly useful for detecting frequency shift keying signals sent over a public switched network.

As shown, an input signal is received on a line 1 and is limited in a clipper 2 to either a high or low-level signal. A clock 3 gates the clipped signal into the first stage of a shift register 4. Shift register 4 is sufficiently long to contain the sample from approximately one full cycle of the lower frequency to be discriminated and is tapped at a point 5 corresponding to the samples from one full cycle of the higher frequency signal. The output signal of shift register 4 on output line 6 is combined in Exclusive OR 7 with the signal from clipper 2 on line 8 and similarly the tapped output on line 5 is combined with the input signal on line 8 in Exclusive OR 9. The output signal of Exclusive OR 7 is gated through an AND 10 to a "countdown" input of a reversible counter 11 and the output of Exclusive OR 9 is gated through an AND 12 to a "countup" input of counter 11. AND 10 is gated by a signal on line 13 through an OR 14 receiving all the "1" signals from counter 11 so line 13 is up except when counter 11 is at its lowest reading. AND 12 is similarly gated by a signal on line 15 from an OR 16 receiving all of the "0" signals from counter 11. These circuits prevent an overflow of counter 11 past either its high or low limit. A line 17 from clock 3 is used to gate the countup or coun...