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A method to tune and modify the resonant frequency using PCB, Package and Chip Lumped RLC model

IP.com Disclosure Number: IPCOM000074384D
Original Publication Date: 2005-Feb-23
Included in the Prior Art Database: 2005-Feb-23
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Abstract

Historically the noise rejection of closed loop PLL has been considered only qualitatively. The need for driving mathematical model and hence providing Quantitative noise rejection curve was always a big concern. The algorithm presented here shows how using Sensitivity Function provides an operating range for any particular design at chosen technology for Noise Budget at each frequency of operation. Further, Sensitivity function shows what gain/budget is ( i.e. -db ) for any disturbance in the range of bandwidth of operation. A new technique claimed by this disclosure is to embed Sensitivity Function driven from closed loop transfer function of PLL with Bode plots to calculate these Noise rejection Curves. These curves can be Used/Applied further as part of the necessary information to better address the system noise budgeting in any unique ASIC Design.

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A method to tune and modify the resonant frequency using PCB, Package and Chip Lumped RLC model

Main Idea

1. Describe your invention, stating the problem solved (if appropriate), and indicating the advantages of using the invention.

Historically the noise rejection of closed loop PLL has been considered only qualitatively. The need for driving mathematical model and hence providing a quantitative noise rejection curve was always a big concern. The algorithm presented here shows how using a Sensitivity Function provides an operating range for any particular design at a chosen technology for a given Noise Budget at each frequency of operation. Further, the Sensitivity function shows what gain versus budget ( i.e. -db ) for any disturbance in the range of bandwidth of operation. A new technique claimed by this disclosure is to embed a Sensitivity Function driven from a closed loop transfer function of PLL with Bode plots to calculate these noise rejection curves. These curves can be used and applied further as part of the necessary information to better address the system noise budgeting in any unique ASIC Design.

2. How does the invention solve the problem or achieve an advantage,(a description of "the invention", including figures inline as appropriate)?

In order to address the problem solving of this invention a short definition of the sensitivity function is needed. Consider a feedback control system in Figure -1 with plant "P" and Controller "G".

Most Frequency Domain ( Small Signal Model ) can be stated in the form of upper bounds defined as a

Sensitivity Function:

S(s) = 1 / [ 1 + P(s)G(s) ] eq(1)

A Complementary Sensitivity Function:

T(s) = [ P(s)G(s) ] / [ 1 + P(s)G(s) ] eq(2)

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and

Q(s) = [ G(s) ] / [ 1 + P(s)G(s) ] eq(3)

Our concern in this disclosure is with equation-1 "eq(1)" as it applies to ASIC PLLs.

Figure - 2 shows Phase-Locked Loop's continuous"S" domain model which is used to drive Sensitivity and Complementry Sensitivity function:

Using Figure - 2 and not cancelling any Pole/Zero from the denominator and numerator we have:

PLL Complimentary Sensitivity Function:

T(s) = [ S x S x ( a1 x S^3 + a2 x S^2 + a3 x S + a4 ) ] / [ S x S x ( b1x S^5 + b2 x S^4 + b3 x S^3 + b4 x S^2 + b5 x S + b6)]

Parameters: a1............a4 and b1 .........b6 are real and unique for each design based on the PLL
reference clock and tuning bits specified.

PLL Sensitivity Function:

S(s) = [ S x S x ( c1 x S^2 + c2 x S + c3 ) ] / [ d1 x S^4 + d2 x S^3 + d3 x S^2 + d4 x S + d4 ]

Parameters: c1............c3 and d1 .........d4 are real and unique for each design based on the PLL
Reference Clock and tuning bits specified.

Two illustrative Numerical examples have been given below to show the application.

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