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Single Pass Error Effect Determination (Speed)

IP.com Disclosure Number: IPCOM000074394D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Godoy, HC: AUTHOR [+2]

Abstract

The technique described enables the implementation of a logic fault simulation program which in a single pass through a series of test patterns calculates the response of the nonfailing logic and determines the effect of all single-failure conditions upon the logic. The technique may be applied within any interpretive logic simulation program (such as the unit-delay simulator illustrated in the flowchart). Modifications are made to the simulator calculation and propagation routines to process lists of failures as well as logic values.

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Single Pass Error Effect Determination (Speed)

The technique described enables the implementation of a logic fault simulation program which in a single pass through a series of test patterns calculates the response of the nonfailing logic and determines the effect of all single-failure conditions upon the logic. The technique may be applied within any interpretive logic simulation program (such as the unit-delay simulator illustrated in the flowchart). Modifications are made to the simulator calculation and propagation routines to process lists of failures as well as logic values.

When a logic block is simulated the nonfailing value for the block is calculated. All the failures that can cause a block value different from the nonfailing machine are placed on a failure list associated with the block. When the output value of a block determines (or controls) the output value of a block it feeds, the list of failures for the first block are included on the lists of failures for the second block. The block values and the list of failures that can alter the block value are thus propagated and subsequent block calculations can consider all the failures that can cause an erroneous output value for the block being calculated.

Note that, during the propagation of failure lists, the same failure may affect more than one input of a logic block because of feedback loops of reconvergent fanout. In such cases the failure is said to have a potential multiple control over the blo...