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Browse Prior Art Database

FET Storage Cell

IP.com Disclosure Number: IPCOM000074413D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+4]

Abstract

This storage cell suitable for use in monolithic storages consists of two cross-coupled FET's.

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FET Storage Cell

This storage cell suitable for use in monolithic storages consists of two cross-coupled FET's.

The standby power required for maintaining the stored information is minimized in that recharging is effected by means of an alternating voltage applied via capacitive-load resistors.

Each of the cross-coupled FET's T1 and T2 is connected to recharging voltage source V via diodes D1 or D2 which is forward biased with respect to the recharging pulses, and via a series connected capacity C1 or C2. D1, C1 and D2, C2 form load resistors. Additionally, in each branch series connection T1 and D1 or T2 and D2 is bridged by means of reverse biased diodes D12 or D22 through which the pulses of V going opposite to the recharging pulses are by- passed.

The leakage current flowing via the leakage resistor from the gate of conductive T1 or T2 is compensated for by V via the associated load resistor. The charging state and thus the stored information are maintained, irrespective of the leakage current. Load resistors C1, D1 and C2, D2 are controllable by the frequency and pulse shape of the voltage of V and are dependent upon the selected switching elements. This ensures minimum standby power for maintaining the stability of the storage cell.

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