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Interruption Mechanism for Multiple Computer Systems

IP.com Disclosure Number: IPCOM000074448D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Rosenfeld, JL: AUTHOR [+3]

Abstract

Communication among processors in a loosely coupled multiple-computer system is established through a modified two-channel switch in an otherwise conventional I/O control unit.

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Interruption Mechanism for Multiple Computer Systems

Communication among processors in a loosely coupled multiple-computer system is established through a modified two-channel switch in an otherwise conventional I/O control unit.

The figure shows two CPU's sharing an I/O control unit, which may be, for example, the control unit of a disk storage facility. It will be assumed that CPU 1 is to interrupt CPU 2. In response to the Start I/O (SIO) instruction issued by CPU 1, the channel of CPU 1 fetches the Channel Address Word (CAW) and the Channel Command Word (CCW) from memory 1 in the usual fashion. When CPU 2 is to be interrupted, the CCW will contain a special command code designated SOC (Signal Other Channel), which passes through the standard interface to the I/O control unit, where it is decoded by the modified two-channel switch to generate an "attention" interrupt on the lines to the channel for CPU 2. The latter channel thereupon generates a Channel Status Word (CSW) with its attention bit set to 1, interrupting CPU 2 and placing the control unit address in the old Program Status Word (PSW). The control unit is disconnected immediately following channel acknowledgment of the attention signal.

The operations peculiar to this concept are the decoding of the special SOC code and the consequent raising of an attention interrupt signal as described. The channel operations are standard. Either CPU can interrupt the other by this means.

Several variations of this...