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Cyclic Address Repowering for Addressing Memory Cells

IP.com Disclosure Number: IPCOM000074456D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Knauft, G: AUTHOR [+4]

Abstract

This arrangement reduces the number of amplifiers needed to amplify the decode signals used in selecting circuits in monolithic memories. Each chip 10 contains a single amplifier 12 which amplifies one of the decode signals. The amplifier 12 has an input terminal and output terminal on the chip so that it can receive the signal to the chip and transmit the amplified signal to other chips 10 of the memory. The chips are identical and, therefore, the inputs to the amplifier 12 must be interchanged if all of the decode signals E1 through En are to be amplified. Thus, input E1 is connected to the input of amplifier 12 on chip 10a and the output of the amplifier 12 is used as a decode input to all the other chips 10b through 10d.

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Cyclic Address Repowering for Addressing Memory Cells

This arrangement reduces the number of amplifiers needed to amplify the decode signals used in selecting circuits in monolithic memories. Each chip 10 contains a single amplifier 12 which amplifies one of the decode signals. The amplifier 12 has an input terminal and output terminal on the chip so that it can receive the signal to the chip and transmit the amplified signal to other chips 10 of the memory. The chips are identical and, therefore, the inputs to the amplifier 12 must be interchanged if all of the decode signals E1 through En are to be amplified. Thus, input E1 is connected to the input of amplifier 12 on chip 10a and the output of the amplifier 12 is used as a decode input to all the other chips 10b through 10d. In a similar manner, the amplifier 12 on chip 10b receives a decode signal E2 and transmits an amplified signal to each of the chips 10a, 10c and 10d. Thus, each of the decode signals E1 through En is amplified while using only a single amplifier 12 on each chip and using identically formed chips
10. In certain applications it may be desirable that amplifier 12 be an amplifier with a true and inverted output, so that the true and complement decode signals can be generated on the chips 10 while still requiring only a single amplifier 12 for each chip 10.

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