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Noise Rejecting Phase Generator

IP.com Disclosure Number: IPCOM000074468D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Dixon, JD: AUTHOR

Abstract

Noise insensitive logic circuitry responds to a single input clock pulse to produce a series of discrete output pulses. The presence of an apparent clock pulse on the input line causes a recirculating internal clock to generate the discrete output pulses with the number of those pulses being selectable by a control signal. The circuitry is particularly useful in association with a disk file where oxide coating defects produce apparent clock pulses which should invoke error handling procedures by the object program.

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Noise Rejecting Phase Generator

Noise insensitive logic circuitry responds to a single input clock pulse to produce a series of discrete output pulses. The presence of an apparent clock pulse on the input line causes a recirculating internal clock to generate the discrete output pulses with the number of those pulses being selectable by a control signal.

The circuitry is particularly useful in association with a disk file where oxide coating defects produce apparent clock pulses which should invoke error handling procedures by the object program. This circuitry permits the object program to invoke error recovery procedures because it invariably generates a sequence of pulses that are initiated by the apparent clock pulse regardless of clock pulse circuitry permits the object program to invoke error recovery procedures because it invariably generates a sequence of pulses that are initiated by the apparent clock pulse regardless of clock pulse error.

Each input clock pulse at 10 causes an output clock pulse at 11. The pulse at 11 is followed by separate discrete output pulses appearing sequentially at 101, 102, 103 and 104 although only 101 and 102 are produced if control input 36 is present. The pulses at 10 can be derived from a data separator clocking circuit which produces 100 nsec signals from recorded disk file data. Assuming that AND 12 is conditioned, latch 13 is set by the presence of input clock 10 which also begins the output clock pulse 11. Latch 14 is set by the set of 13 which thus removes the inhibit generated by inverts 15 and 17 through 0R 16. The delay line oscillator composed of AND 18, invert 19 and delay 20 is thus gated to commence producing pulses. Further, the set of 14 will place a pulse in the first stage 21 of a phase ring through AND 22 since input 25 initiates stage 21, 26, 28 and 30 are clear. Shortly thereafter, the output of 20 will appear and thus complete the conditioning of AND 23 to start first output pulse 101. The drop of invert 15 output and the start of 101 causes latch 24 to set, thereby resetting latch 13 and terminating output clock pulse 11 while deconditioning 1...