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Scanning a Bit Significant Register

IP.com Disclosure Number: IPCOM000074469D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Davis, MI: AUTHOR [+3]

Abstract

The logical condition of the bit positions within a register are scanned sequentially so that only bit positions having significant data produce a scanning response output, while bit positions containing nonsignificant data are bypassed.

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Scanning a Bit Significant Register

The logical condition of the bit positions within a register are scanned sequentially so that only bit positions having significant data produce a scanning response output, while bit positions containing nonsignificant data are bypassed.

Register 10 is initially loaded with a byte of data wherein each bit position of that byte has significance independent of the logical condition of the other bit positions. Each byte loaded into 10 can occur in any combination and a scan for logical 1's will be assumed. After 10 has been loaded, some minimum amount of logic circuit delay time is permitted to elapse before a start pulse is introduced at terminal 11. The circuitry shown will then effectively scan in sequence from bit position 0 through bit position 3 of 10. No time is wasted scanning higher bit positions which contain a logical 0 so that detection of the first logical 1 is accomplished in one logic circuit delay time regardless of the bit position in which it occurs. Each bit position of 10 is intended to control the performance of a specified function and, once that function is performed, the scan continues. Again, the transition time from any logical 1 to the next logical 1 or the scan completion is a constant logic delay regardless of the relative bit positions which contain the logical 1's. That is, transition time between adjacent bit positions is no less than the transition time between the highest and lowest-order bit positions.

Assuming a 1 has been stored in position 0 of 10 and a start pulse 11 has set flip-flop 12, AND 14 will be completely conditioned...