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Adjustable Pulse Delay/Width Circuit

IP.com Disclosure Number: IPCOM000074470D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Benedict, QL: AUTHOR [+4]

Abstract

This circuitry responds to an input pulse to product an output pulse having a controllable width and time delay relative to the input pulse. The circuit uses two adjustable delay circuits, one of which provides a feedback for controlling the pulse width while the other responds to the initial pulse to produce the delay.

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Adjustable Pulse Delay/Width Circuit

This circuitry responds to an input pulse to product an output pulse having a controllable width and time delay relative to the input pulse. The circuit uses two adjustable delay circuits, one of which provides a feedback for controlling the pulse width while the other responds to the initial pulse to produce the delay.

Input pulse 10 is coupled to set AC trigger 11 which produces an energizing level for adjustable RC delay circuit 12. When the output level of 12 reaches the threshold level of inverter 15, this signal is transmitted through the inverter-buffer 16 to the output 18. In addition, the output of 15 is coupled through diodes 19 and 20 into adjustable RC delay circuit comprised of capacitor 21 and resistances 22 and 23. Eventually the output of this adjustable feedback RC circuit will reach a level at 25 sufficient to reset 11, thereby producing the falling edge of the output pulse at 18 and the circuit is ready to receive another input pulse 10.

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