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Program Controlled Test Adapter

IP.com Disclosure Number: IPCOM000074476D
Original Publication Date: 1971-Apr-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Kemmerer, KK: AUTHOR [+2]

Abstract

The adapter provides an interface between a host CPU and digital devices to be tested, with this adapter being software and/or hard ware configurable for accommodating connections to a wide variety of devices. The adapter utilizes logic circuitry and a program board to convey digital data between the host CPU and the device under test, with the program board being preset to meet the particular requirements for connecting to the device to be tested. Thus, the same host CPU and essentially the same adapter can be used to perform tests upon almost any digital equipment including I/O devices, other processors or the like.

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Program Controlled Test Adapter

The adapter provides an interface between a host CPU and digital devices to be tested, with this adapter being software and/or hard ware configurable for accommodating connections to a wide variety of devices. The adapter utilizes logic circuitry and a program board to convey digital data between the host CPU and the device under test, with the program board being preset to meet the particular requirements for connecting to the device to be tested. Thus, the same host CPU and essentially the same adapter can be used to perform tests upon almost any digital equipment including I/O devices, other processors or the like.

Host CPU 10 includes stored programs capable of testing/simulating any digital functional unit. The interface adapter is coupled to bus out 11 of 10 as well as to bus in 12. Decoder 15 is coupled to be controlled by signals on 11. If the interface adapter is separately addressable, 15 includes detection circuitry for detecting when its address is on 11, but in many circumstances this addressing feature is not required. Essentially 15 is arranged to respond to either Control or Sense commands. A Control command typically results in a signal being produced on lines 16 and/or 17 so as to enable an appropriate digital register through AND's 18 - 20 and/or AND's 21 - 23. Thus, 15 could respond to a first command from 10 by enabling 18 - 20 so that the byte placed on 11 by 10 would be stored in a first register composed of latches 24 - 26 whereas a subsequent command might enable 21 - 23 so that a second register comprised of latches 27 - 29 could be set from a subsequent byte. Of course, both 24 - 26 and 27 - 29 could be concurrently set if desired. Program board 30 is arranged so that appropriate connections can be selected between output terminals from the registers such as 31 and/or 34 - 35 to preselected terminals associated with output 40 which is ultimately connected to the device to be tested. For instance, if driver circuit 46 provides an appropriate level directly, a jumper might be connected d...