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Micro Instructions

IP.com Disclosure Number: IPCOM000074483D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 5 page(s) / 67K

Publishing Venue

IBM

Related People

Resnick, SA: AUTHOR [+4]

Abstract

This description is directed to three micro-instructions which are advantageously employed in microprogram test and control operations.

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Micro Instructions

This description is directed to three micro-instructions which are advantageously employed in microprogram test and control operations.

A first of these instructions, suitably termed the RR* microinstruction, enables the testing for a set of "1" and a set of "0" bits in a source field. The results of these two tests are logically combined to determine the field which is to be employed to operate on the destination field.

The source field is used to operate on the destination field if the specified logical combination of the source field test results are satisfied. Otherwise, an all-zero field is employed to operate on the destination field. The field operating on the destination field can be either directly inserted into the destination field or can be ORed bit-by-bit into the destination field.

The source field is tested for a set of "1" bits corresponding in position to "1" bits in an R-mask and is simultaneously tested for a set of "0" bits corresponding in position to "1" bits in an R* mask. Bit positions in the source field that are to be ignored, i.e., not tested for, have the corresponding bit position in both of the R and R* masks' zero. When both the R and R* masks contain all "0"s, the micro- instruction corresponds to an eight-bit (byte) field move.

The two results of the source field tests can be logically ANDed, ORed, or XORed together. If the logical function is satisfied, then the source field is employed to operate on the destination field. Otherwise, an all-zero field is used to operate on the destination field. When the test results are ANDed together, both the specified set of "1" bits and the specified set of "0" bits have to be present in the source field to satisfy the logical AND functions. When the test results are ORed together, either or both of the specified set of "1" bits and the specified set of "0" bits must be present in the source field to satisfy the logical OR functions. When the test results are XORed together, either one, but not both, of the specified set of "1" bits or the specified set of "0" bits have to be present in the source field to satisfy the logical XOR functions. If the specified logical function is not satisfied, then an all-zero field is employed to operate on the destination field.

In the use of this micro-instruction, the source fields can range over the functional concatenation of a first group of registers in a computer and the destination fields can range over the functional concatenation of a second group of registers in a computer. The fields can have a chosen bit width, suitably one byte. Thus, the RR* micro-instruction can use any byte field in the first group of registers and the status latches (also 1 byte) for a source field and any byte field in the second group of registers for a destination field.

In Fig. A, there are shown bit assignments, source fields, and destination fields for the RR* micro-instruction. The latter instruction is 32-bits wide...