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Complementary Four Device FET Memory Cell

IP.com Disclosure Number: IPCOM000074498D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Gaensslen, F: AUTHOR

Abstract

The operation of the complementary four device memory cell shown in A is discussed in detail in U.S. Patent 3,535,699 in the names F. H. Gaensslen and D. P. Spampinato and assigned to IBM. In essence, the backward biased diode portion 1 of transistor T2 and the backward biased diode portion 2 of transistor T1 act as a voltage divider in stand-by, with diode 2 of device T1 being of such impedance that substantially all the voltage due to the flow of leakage currents from +V(SB) is dropped in backward biased portion 2 of device T1. This voltage drop which is applied to node N1 and to the gate 3 of device T3 maintains that device in the ON or conducting condition. In a similar manner, because T3 is conducting, ground potential is maintained at node N2 causing device T1 to remain in the OFF or nonconducting condition.

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Complementary Four Device FET Memory Cell

The operation of the complementary four device memory cell shown in A is discussed in detail in U.S. Patent 3,535,699 in the names F. H. Gaensslen and
D. P. Spampinato and assigned to IBM. In essence, the backward biased diode portion 1 of transistor T2 and the backward biased diode portion 2 of transistor T1 act as a voltage divider in stand-by, with diode 2 of device T1 being of such impedance that substantially all the voltage due to the flow of leakage currents from +V(SB) is dropped in backward biased portion 2 of device T1. This voltage drop which is applied to node N1 and to the gate 3 of device T3 maintains that device in the ON or conducting condition. In a similar manner, because T3 is conducting, ground potential is maintained at node N2 causing device T1 to remain in the OFF or nonconducting condition.

The memory cell of the patent operates on the assumption that during stand-by the total leakage current in-flow exceeds the out-flow in order to keep the high impedance node N1 from discharging. The appropriate ratio of leakage currents can be easily obtained by placing Schottky barrier diodes (SBD) of suitable barrier height in parallel with regions 1 of the P channel devices T2 and T4.

A low enough barrier height of the SBD easily insures compensation of the current out-flow which means no loss of charge on the high impedance node N1 during stand-by.

Drawing B shows the physical embodiment of this circuit arra...