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Browse Prior Art Database

Wiring Parallator

IP.com Disclosure Number: IPCOM000074503D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Hedeman, PT: AUTHOR [+2]

Abstract

A three-dimensional conductor pattern for a multichip integrated circuit substrate enables the circuit designer to readily wire around existing printed circuit lines on the device side of the module.

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Wiring Parallator

A three-dimensional conductor pattern for a multichip integrated circuit substrate enables the circuit designer to readily wire around existing printed circuit lines on the device side of the module.

The plastic substrate body 9 shown in Drawing A is injection molded about the spaced pattern of parallel, buried conductors 3. Each of the conductors 3 (see also Drawing B) has uniformly spaced along its length, laterally disposed tabs 4, each of which is bent at 10 as to be perpendicular to the plane of the pattern of conductors 3. Tabs 4 are exposed on the surface of the device side of substrate 9 so that electrical contact may be made with anyone of the printed circuit conductors 7. By this means each of the conductors 3 serves as an optional underpass conductor permitting greater flexibility in the printed circuit conductor layouts interconnecting monolithic chips 1 and 2.

Although Drawing A shows the parallator concept as applied to a pin array module, the buried bypass conductor concept is equally applicable to dual-in-line packages. Also, in a dual-in-line package, the end of conductor 3 can be extended longitudinally so as to emerge from the side of the substrate body 9, in which configuration conductor 3 serves the dual function as a buried bypass conductor and as an I/O lead. In addition, the material comprising substrate body 9 need not be limited to injection molded plastics but can be extended to other conventional packaging materials s...