Browse Prior Art Database

Three Device Random Access Memory

IP.com Disclosure Number: IPCOM000074511D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Sumilas, JW: AUTHOR [+2]

Abstract

The circuit of the figure is a two-dimensional array of insulated gate field-effect transistor cells with separate bit and sense lines and which can be used to provide a nondestructive read integrated circuit memory, having a bootstrap storage capacitor referenced to the sense line thereby providing the capability of the circuit to sense the information source and regenerate it with a simpler pulse sequence and in shorter time.

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Three Device Random Access Memory

The circuit of the figure is a two-dimensional array of insulated gate field- effect transistor cells with separate bit and sense lines and which can be used to provide a nondestructive read integrated circuit memory, having a bootstrap storage capacitor referenced to the sense line thereby providing the capability of the circuit to sense the information source and regenerate it with a simpler pulse sequence and in shorter time.

Each cell consists of a storage capacitor 1 coupled between a sense line 2 and a source 3 of an input isolation transistor 4, whose gate 5 is coupled to a write line 6 and whose source 7 is connected to a bit line 8. The gate 9 of a storage transistor 10 is also connected to capacitor 1. The drain 11 of transistor 10 is connected to a read line 12 to which is also connected the gate 13 of an output isolation transistor 14, whose source 16 is connected to sense line 2 and whose drain 15 is connected to the source of transistor 10. Transistors 10 and 14 thus form the usual AND gate for sensing purposes.

When in array form, only the cells which are selected by the control lines are operative during a read or write cycle and any other cells in the array are isolated by transistors 4 and 14. Transistor 4, when activated during a write cycle, controls the state of storage transistor 10 by permitting the bit line drive to set the appropriate voltage on capacitor 1, while transistor 14, when activated during a re...