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Metal Insulator Trap Oxide Semiconductor Memory Cell

IP.com Disclosure Number: IPCOM000074512D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+3]

Abstract

A nonvolatile, low-voltage, high-speed, write-read semiconductor type memory cell has been devised. The FET device of the figure utilizes a four-layer gate structure 11, disposed on the surface 12 of a silicon substrate 13 into which source 14 and drain 15 diffusions are made. The gate structure 11 is disposed over the channel region 10 between the source and drain diffusions and consists of a layer of silicon dioxide 16 approximately 20 Angstrom thick overcoated with a layer of trap material 17, such as silicon nitride about 10-100 Angstroms in thickness, over which there is deposited a high-dielectric insulator material 18 such as titanium dioxide and a metal gate electrode 19.

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Metal Insulator Trap Oxide Semiconductor Memory Cell

A nonvolatile, low-voltage, high-speed, write-read semiconductor type memory cell has been devised. The FET device of the figure utilizes a four-layer gate structure 11, disposed on the surface 12 of a silicon substrate 13 into which source 14 and drain 15 diffusions are made. The gate structure 11 is disposed over the channel region 10 between the source and drain diffusions and consists of a layer of silicon dioxide 16 approximately 20 Angstrom thick overcoated with a layer of trap material 17, such as silicon nitride about 10-100 Angstroms in thickness, over which there is deposited a high-dielectric insulator material 18 such as titanium dioxide and a metal gate electrode 19.

Metal electrode 19 serves as a control gate. Insulator 18 is used to prevent a short between the gate electrode 19 and the trap material 17. Insulator 18 should have a dielectric greater than 50 in order to keep the operating voltage low, while trap material 17 should contain a high density of trap states for electrons which are spatially distributed and whose energies preferably occur within the band gap of the semiconductor. This FET has two states or threshold voltages that are determined by the presence or absence of electrons in the trapped states. The high dielectric of insulator 18 assures that a significant portion of the gate potential is applied across layers 16 and 17 resulting in high- speed charging of the trap states in t...