Browse Prior Art Database

Reduction of I/O Caused CPU Delays

IP.com Disclosure Number: IPCOM000074566D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Thorn, CA: AUTHOR

Abstract

As the instruction execution rates of central processing units (CPUs) become higher, the effect of CPU delays due to I/O operations becomes more serious. One of the causes of the delay is when an I/O instruction, such as start I/O, is held up while the I/O interface sequence initiated by the instruction is completed. This sequence is usually a full initial selection sequence (defined in Beausoleil et al. patent 3 336,582) requiring about ten-interlocked signal exchanges.

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Reduction of I/O Caused CPU Delays

As the instruction execution rates of central processing units (CPUs) become higher, the effect of CPU delays due to I/O operations becomes more serious. One of the causes of the delay is when an I/O instruction, such as start I/O, is held up while the I/O interface sequence initiated by the instruction is completed. This sequence is usually a full initial selection sequence (defined in Beausoleil et al. patent 3 336,582) requiring about ten-interlocked signal exchanges.

In order to release the CPU without waiting for the interface sequence, a means is provided for signalling to the CPU all the conditions discovered at the device during the interlace sequence. This is accomplished by a new instruction called START I/O FAST RELEASE defined for IBM System/370 (see IBM System/370 Principles of Operation, form GA22-7000-0, June 1970) which causes the status portion of the channel status word (CSW) to be replaced. With this instruction, the operation proceeds in a manner similar to a START I/O operation defined for System/360, except that if the channel and subchannel are operational and not busy, the channel address word (CAW) is fetched and, if valid, the start I/O operation is released immediately with a condition code of 0, thus freeing the CPU. The channel then fetches the channel command word (CCW) at the address specified by the CAW and the channel initiates an initial selection sequence over the I/O interface. If the initial...