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CTE Balancing to Improve FCBGA Second Level Interconnect Thermal Fatigue Life

IP.com Disclosure Number: IPCOM000074576D
Publication Date: 2005-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that introduces a CTE balancing concept to improve FCBGA package second level interconnect (SLI) thermal fatigue.

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CTE Balancing to Improve FCBGA Second Level Interconnect Thermal Fatigue Life

Disclosed is a method that introduces a CTE balancing concept to improve FCBGA package second level interconnect (SLI) thermal fatigue.

Background

Solder joint thermal fatigue failure in FCBGA packages is associated with a CTE mismatch between the package and the board. Package CTE is significantly lower than the board CTE, due to a silicon die and underfill (see Figure 1). This CTE mismatch results in different levels of thermal expansion between the package and board, and introduces strains on the solder joint. In hot and cold operating conditions, a phenomenon called thermal fatigue occurs.

General Description

The disclosed method introduces a CTE balancing concept to improve FCBGA package SLI thermal fatigue. The CTE balancing is achieved by attaching an appropriate material (such as a CTE balancer) directly on bottom side of the package (see Figure 2).

Advantages

The disclosed method is a board level point solution to improve FCBGA package SLI thermal fatigue life.

       
   

Package CTE (Silicon +underfill +substrate)

 ~ 5ppm/degK (estimated)

 
 
   
 

Fig. 1

       
   
   

A lower CTE material attached firmly to reduce board CTE . End goal is to balance up Package and board CTE for thermal fatigue improvement.

 
 
 

Fig. 2

Disclosed anonymously