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Self Organizing Storage

IP.com Disclosure Number: IPCOM000074590D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+3]

Abstract

In a data processing system consisting of processing and storage elements, it can be useful to have storage elements perform operations listed below with minimal interaction by the processing elements: 1) Accept a fetch/store request while responding to an operation of the opposite type (i.e. initiate a store while executing a fetch). 2) Move variable length fields of data between contiguous storage spaces. 3) Swap data between contiguous storage spaces. 4) Clear a group of contiguous spaces. 5) Concatenate data in a group of contiguous spaces with a constant value or with another memory space with contiguous addresses. 6) Perform the above on noncontiguous memory spaces having constant address separations.

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Self Organizing Storage

In a data processing system consisting of processing and storage elements, it can be useful to have storage elements perform operations listed below with minimal interaction by the processing elements: 1) Accept a fetch/store request while responding to an operation of the opposite type (i.e. initiate a store while executing a fetch). 2) Move variable length fields of data between contiguous storage spaces. 3) Swap data between contiguous storage spaces. 4) Clear a group of contiguous spaces. 5) Concatenate data in a group of contiguous spaces with a constant value or with another memory space with contiguous addresses. 6) Perform the above on noncontiguous memory spaces having constant address separations.

The illustrated configuration performs such operations with minimal effect upon the central processing unit. This is accomplished by relegating to the memory elements, to varying degrees, instruction processing hardware. Fig. 1 illustrates the system logic required for basic operation. The registers in the storage element consist of a store memory address register (SMAR), a fetch address register (FMAR), a count register (CNTR), memory sense latches (SL), and memory data registers (MDR-E and MDR-I).

For the function specified above at 1, the memory system is equipped with two busy condition circuits; fetch busy and store busy. When the processor initiates a fetch instruction, the fetch address is transferred to FMAR, the fetch busy line is conditioned, and the memory is started. If there is a subsequent store request from the processor, the store address is transferred to SMAR and the store data to MDR, ignoring the fetch busy condition. When the fetch request has been honored, the store operation is initiated without further interaction with the processor. The sequence of store before fetch is executed in a similar manner.

To move a contiguous block of memory data from one storage location to another, SMAR and FMAR are implemented as counters which can be either incremented or decremented. The processor loads FMAR with a starting address of the contiguous memory field to be moved, SMAR with a starting address of the recipient contiguous address field and CNTR with the number of addresses to be transferred. The processor is then relieved of further interaction and the memory system completes the operation as follows.

A word fetched from the address of PMAR is transferred to the sense latches and MDR-I. Next the word is stored in the address specified by SMAR and CNTR is incre...