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A Routable Spacer for Stacked Flip Chip and Wire Bond Die

IP.com Disclosure Number: IPCOM000074603D
Publication Date: 2005-Feb-23
Document File: 2 page(s) / 49K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a stacked die spacer that allows for flexible designs, a low-cost redistribution of pad layouts, and lower profile die stacking. Benefits include reducing through-put time and simplifying the assembly.

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A Routable Spacer for Stacked Flip Chip and Wire Bond Die

Disclosed is a method for a stacked die spacer that allows for flexible designs, a low-cost redistribution of pad layouts, and lower profile die stacking. Benefits include reducing through-put time and simplifying the assembly.

Background

Die stacking is crucial for small form factor micro-electronic packaging; however, there are current issues associated with die stacking. First, the stack-up height can take up too much space within the design. Second, stack-up and die overhang assembly stresses can affect the performance of micro-electronic devices. Third, the stacking of similar die is difficult because of the bond pad arrangements.

Currently stacked die are combined with their wire bond pads face-up.  In order to stack similar die, a mechanical spacer is used to allow enough space between the die for wire bonding
(see Figure 1).  Alternate solutions use internal or external redistribution routing layers (i.e. traces that span the die and reroute the bond pads to new locations). The die is then offset to allow for alternate corner bonding.

General Description

The disclosed method uses a routable spacer that enables the die to be connected electrically through pads on the spacer surface (see Figure 2); this is accomplished through interconnects, such as solder ball (i.e. flip chip) thermo-compression bonding. Electrical connections are made internally to the spacer and routed to the peripheral pads on the spacer i...